Several methods are known to illuminate a photoresist on a wafer. According to a first method, a stepper is used to illuminate the wafer. According to another method, a single mask for a wafer is used. Thereby, only one exposition per wafer is required.
In a typical process, a photostructurable polymer is spun onto the wafer by a spinning-process such that the polymer with a thickness in the micrometer range is obtained. Other methods are used as well to bring a photostructurable polymer onto a wafer, for example coating with a laminated dry film.
For photolithography, a mask is placed above the wafer and illuminated from above. The mask usually has a substrate made of glass, whereas the defining structures are made of a chrome layer on the bottom side of the mask. In a so called mask aligner, light is coming from a light source and through an optical system towards the mask. The light is blocked at the chrome layer of the mask, but it is passing the areas not covered by chrome. The mask is usually of a square format, whereas the length of the square is some centimeters larger than the diameter of the wafer, so that the mask holder of the aligner does not interfere with the wafer or the optical path of the light. Thus, the mask can be of a round format, as long the outer diameter is larger than the diameter of the wafer, so that the mask holder of the aligner does not interfere with the wafer or the optical path of light.
The light that passes through the mask initiates a photochemical reaction on the resist. In a positive-type resist, the exposed area is removed after development, in a negative-type resist, the non-exposed areas are removed after development. The resolution of structures is limited by the diffraction of light at the chrome structures of the mask. The light passing through the chrome structures is bent at these structures. While the incoming light at the mask can be considered as parallel, the light passing through the mask is not parallel anymore and is diverging.
The relationship between the gap and the resolution of the resist can be approximated by a critical distance CD. The critical distance CD, that is the smallest feature that can be achieved by using a mask aligner operated under the gap s is given by the following relationship:
      CD    min    ≈                    λ        ⁡                  (                      s            +                                          1                2                            ⁢              t                                )                      .  
Herein, CD is the critical distance, lambda (λ) is the wavelength of the light used for exposure, s is the gap width between the mask and the wafer and t is the thickness of the resist. It can be seen quantitatively that the critical distance increases with a higher gap t and thus the resolution decreases.
This diffraction of light limits the resolution and accuracy of the lithography process. It is desirable to minimize the effect of diffraction to reproduce structures with the highest possible contrast to have well defined features in the resist.
The diffraction of the light at the chrome layer cannot be avoided fully, but it can technically be minimized to an acceptable level. This is done by minimizing the “gap”, the distance between the mask and the wafer. By doing so, the impact of the diffraction is kept under control. Typically, the gap is kept at only 20-80 μm. It is also possible to have essentially no gap, which is called “full contact mode”. Here, the diffraction is minimal.
Apart from mask aligners and steppers, other optical systems by which lithography can be done are known. Projection systems do not use parallel light, but use an optical set up that projects the pattern of the mask onto the wafer—in this set up, the diffraction is minimized, yet not eliminated, and the mask can be placed at a wider distance to the wafer.
For certain application of semiconductors, it is desirable to have lithographic structures on both sides of the wafer. Such applications include Through Silicon Via applications, which are characterized by having integrated circuits on the one side, electrical structures on the other side, and electrically conductive structures through the Silicon to electrically connect both sides.
For such TSV applications, it is furthermore desirable to minimize the thickness of the Silicon wafer. The reason for this is mainly driven by the fact that the chips that are generated from these TSV wafers will later be assembled into stacks. Typically, the desired Silicon thickness is less than 150 μm. If Silicon is thinned to this thickness, it becomes very brittle and bends under its own weight.
To overcome the problem of thin Silicon, carrier-less systems have been proposed in the state of the art. Common characteristic of these concepts is that the wafer is reinforced by a structure at the rim, whereas the centre portion of the wafer is thinned to the desired thickness. The reinforcement structure at the rim gives the wafer enough mechanical stability, whereas the central portion can be very thin. In the context of this application, a thinned wafer with such a support structure at the outer rim is also referred to as a “rim wafer”.